The present invention relates generally to computer systems and, more particularly, to a method and apparatus for maintaining JTAG component descriptions in a nonvolatile memory associated with the components such that a controlling JTAG system can control the components in accordance with standard JTAG operations without prior knowledge of the components.
The Institute of Electrical and Electronics Engineers, IEEE, has standardized a serial test bus for testing integrated circuit components, their interconnections on a printed circuit board and for observing or modifying circuit activity during normal operation of the components. The standardized bus is designated as the IEEE Std 1149.1 and was developed by a Joint Test Action Group, JTAG, composed of members from both Europe and North America such that it is often referred to as an 1149.1 or a JTAG bus.
The introduction of this standard has opened many new areas of opportunity for improved testing and control within computer systems. However, in order to perform testing and other operations via a JTAG bus, it is necessary for a JTAG controller to know how a boundary scan path defined by the standard is configured and also the characteristics of components which are in the scan path if multiple components are interconnected and to be tested. The boundary scan path and component characteristic knowledge is particularly critical since different vendors may implement JTAG technology differently within the specifications of the 1149.1 standard.
There is thus a need for providing JTAG information about a component or a series of components including JTAG technology such that a JTAG controller can properly interface with and control the JTAG technology without having to be programmed with such information.